Core Engineering Capabilities
Hardware System Architecture
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- Full-Cycle Development: Contributed to projects from schematic through validated hardware, including a lidar motherboard, a carrier board built around a Xilinx daughter board, and its automotive Ethernet PHY interface (TI DP83TG720).
- Systems-Level Debugging: Diagnosed a sensor-and-circuit integration failure down to amplifier topology on an independent research project, where subsystems passed individually but failed once combined, a lesson in validating at the system level, not just the block level.
- Applied Platform Design: Extending this schematic-to-bring-up methodology to full high-speed platform builds on Toradex’s open reference carrier boards.
Carrier board references (Dahlia, Apalis) and the Toradex Pinout Designer tool are named here with permission from Toradex (toradex.com).
High-Speed PCB Layout
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- Stackup & Material Selection: Trained in PCB material selection and multi-layer stackup design for controlled impedance and high-speed performance, including dielectric and surface finish trade-offs.
- High-Speed Digital Layout: Studied advanced layout techniques for DDR3, PCIe, SATA, and Ethernet interfaces, applying differential pair routing and length matching through the Dahlia and Apalis carrier board reference designs.
- EMC-Aware Layout & Shielding: Trained in PCB layout, shielding, and filtering techniques for good EMC performance, designing interference out rather than fixing it after the fact.
- High-Speed Signal Classing: Using Altium Designer’s xSignals to organize and manage high-speed nets across board layouts.
SI/PI Analysis & Simulation
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- Reflection & Crosstalk Analysis: Trained in predicting and quantifying reflections, crosstalk, and ground bounce to keep total signal-integrity impact within a system’s noise margin.
- Power Delivery & Noise Margin: Studied power delivery network analysis for supply and ground bounce (SSN), decoupling strategy, and setting routing rules from a noise margin budget, including power supply measurement fundamentals.
- EMC Compliance Fundamentals: Trained in EMC testing methods, including bench-top near-field probe testing and system-level EMC engineering practices.
- Simulation Tools: Circuit-level simulation and validation in LTspice, TINA-TI, and PSpice; working knowledge of HyperLynx’s interface for SI/PI analysis, self-taught and now applying it to real board designs.
Precision PCB Interface for a Piezoelectric Vibration Monitoring System
An 8 Revision Master’s Project: Capturing Picoamp Signals on a Gigaohm Node
A Vibration Monitoring System (VMS) is, at its core, a sensing-and-acquisition chain: a transducer that converts mechanical motion into an electrical signal, an analog front-end that amplifies and conditions that signal without degrading its noise floor, and an embedded interface that digitizes it for storage or display. For my master’s thesis, I designed and built all three stages—a piezoelectric MEMS accelerometer as the transducer, a custom interface circuit as the analog front-end, and a microcontroller-based acquisition layer closing the loop. However, the project’s real center of gravity was the PCB itself: getting a picoamp-level signal off a gigaohm-impedance node and onto a board without the board destroying it.
The Illusion of the Schematic
The interface circuit was the harder half. Because a piezoelectric sensor’s raw output is a tiny charge rather than a voltage, I built and compared multiple amplifier stages, benchmarking op-amps against each other for noise and bandwidth. I cascaded a front-end amplifier with a differential stage to reject common-mode noise, followed by a low-pass filter to cut everything above the signal band. On paper, that circuit was done in a week. On a physical board, it took eight revisions.
Combating Leakage Current in the Copper
At gigaohm-level input impedances, the enemy isn’t noise from the sensor—it is leakage current crawling across the board itself. A trace-to-pad resistance of 100 GΩ sitting next to a 5V rail can leak roughly fifty times more current than the amplifier’s own bias current needs to function correctly. No amount of careful component selection fixes that; only the layout can.
Versions 1.0 & 2.0: Version 1.0 shared a single 5V rail across every amplifier stage, making debugging impossible. Version 2.0 added a guard ring, but on a board too large to drive it properly.
Versions 3.0 to 6.0: I split each amplifier onto its own small board, which solved the leakage but reintroduced parasitics through the cabling between them. It took until version 6.0 to work out that the guard ring needed to be driven by a pure DC bias, not the AC signal I had originally assumed.
Version 7.0 & The Final Stack: I learned the hard way that a single missing ground-copper pour on the top and bottom layers could undo everything else that was right. Restoring it on a 4-layer stack with dedicated analog- and digital-ground shielding is what finally got the module down to 2.7cm × 2.7cm and working.
Validation & The Final Takeaway
Getting the pieces to agree took intense debugging. The circuit worked on the bench, and the sensor worked on the bench. Combined, the response didn’t match either until the front-end topology was reworked to behave as one unified system with the board underneath it. I validated the finished module on a shaker table against a reference accelerometer, then end-to-end with hand-pulse vibration tests feeding a microcontroller and a live readout.
A guard ring works by holding every node around a sensitive one at the same potential, so there is no voltage difference left to leak across—a fix that lives entirely in the copper, not the schematic. That gap between a circuit that is correct on paper and a board that actually behaves the same way in your hands is what pulled me toward PCB design as a specialty in its own right.
A guard ring fix lives entirely in the copper, not the schematic. That gap between a circuit that works on paper and a board that works in your hands is what pulled me toward PCB design as a specialty.
Hardware Track Record
